Auviz Systems provides Middleware IP for the Data Center and Internet of Things. Auviz Systems empowers software and hardware developers through IP and services. Auviz IP delivers higher performance, greater productivity with targeted performance optimizations. Initially targeting FPGA’s, Auviz Middleware IP enables cross platform portability while delivering higher performance per watt.
Auviz Middleware IP is highly optimized for Xilinx Series 7 FPGAs. The Middleware IP is available as synthesizable, C functions for HLS users, OpenCL for Embedded developers, or IP Integrator blocks for traditional RTL users. Customers on different design flows can use AuvizCV IP to design and get to market faster.
Creating end applications using Auviz Systems’ Middleware IP is easy because we have done the hard work of optimizing algorithms on the FPGA already! It is now as simple as calling the functions from your C/C++ program using our API. You can use the OpenCL platform model to call the API from your embedded code, or use HLS to call the API for a more traditional flow. Check out some examples below, or get in touch with us to get more specific.
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Why Auviz Middleware IP?
Auviz Partners help complete our vision and products by enabling our technology through joint development, industry associations and distribution. Xilinx is the leading FPGA supplier is an investor and development partner. The Embedded Vision Alliance mission is to enable and inspire developers to rapidly integrate embedded vision into their applications and inspired the founders to start Auviz Systems. Electro Source and Genesis Associates are Value Added Resellers and work with us to provide complete solutions for our customers.